1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to arrangement of peripheral electrodes, internal electrodes, and internal lines of semiconductor chips.
2. Description of the Related Art
Demand for smaller, thinner, and lighter products is high in the area of electrical devices such as mobile phones, digital cameras, and notebook computers. Accordingly, development of smaller, thinner, and lighter semiconductor components used in the electrical devices with low production costs is an important subject for study.
Recently, BGA (ball grid array) and CSP (Chip Scale Package or Chip Size Package) have been increasingly developed and already put into practical use in some cases. The BGA and CSP are smaller packages that replace conventional IC packages such as TQFP (Thin Quad Flat Package) and TSOP (Thin Small Outline Package). Further, in order to achieve more compact and higher density mounting, widespread use of semiconductor mounting technology (connection technology) using bare chip mounting process with a flip-chip method is strongly desired.
Conventional bare chip mounting with the flip-chip method forms bumps on electrode pads of a semiconductor chip. Recently, however, such a technique has been increasingly used that rewires a semiconductor chip and forms land pads where bumps will be placed with a pad pitch designed as wide as possible to simplify the mounting. This technique is similar to those used for BGA and CSP mounting.
FIG. 9 shows an example of a semiconductor chip conventionally used for semiconductor devices employing the above technique. The semiconductor chip 10 shown in FIG. 9 has a plurality of peripheral electrode pads 1 on its periphery. The peripheral electrode pads 1 are connected to internal circuits (not shown) formed in the semiconductor chip 10 by internal lines (not shown). The peripheral electrode pads 1 are also connected to land pads 3 where bumps will be placed by rewired lines 2. The land pads 3 and the rewired lines 2 are formed by rewiring the chip. The land pads 3 that are pads for mounting solder balls are arranged uniformly on the semiconductor chip 10.
The above chip, however, has the following problems. In higher density mounting, the number of rewired lines 2 arranged between the land pads 3 increases; accordingly, the chance of short-circuit between two rewired lines 2 or between the rewired line 2 and the land pad 3 increases. For example, the rewired line 2 and the land pad 3 are short-circuited in the portions P, Q, and R in FIG. 9.
A technique for solving the short-circuit problem of the rewired lines 2 is disclosed in Japanese Unexamined Patent Application Publication No. 2000-208512. According to this technique, the electrodes having the same function share a single rewired line, thereby reducing the number of rewired lines.
Another problem of the above chip is that the land pads 3 and the internal circuits are connected via the peripheral electrode pads arranged on the periphery of the semiconductor chip 10, and hence the line lengths are long. The long line lengths lead to adverse impacts such as signal delay, line interference, and increased noise. The adverse impacts are significant in high-frequency semiconductor chips that are now increasingly used, creating crosstalk noise or resonance shift.
In the technique described in Japanese Unexamined Patent Application Publication No. 2000-208512, whether the short-circuit problem of rewired lines can be solved depends on the number of electrodes having the common function, and hence the short-circuit problem cannot be solved in all semiconductor devices. Besides, the line lengths cannot be reduced, and thus the problem of adverse impacts such as signal delay also cannot be solved.